1. Field of the Invention
The present invention relates to cache memories, and more particularly, to a cache memory device including a word line driver circuit and method capable of increasing operational speed and yielding a reduction in the chip area of a semiconductor integrated circuit.
2. Description of the Related Art
A typical computer system includes main memory, such as dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), and cache memory. Each memory cell block in the cache memory has an inherent tag address, and each tag address is checked to determine whether it is the same as an address received from a central processing unit (xe2x80x9cCPUxe2x80x9d). Content addressable memory (xe2x80x9cCAMxe2x80x9d) is used in comparing each tag address with an address received from the CPU. In general, the case where a tag address is the same as an address input from a CPU is called a xe2x80x98hitxe2x80x99, and the reverse case is called a xe2x80x98missxe2x80x99.
FIG. 1 is a schematic block diagram of a typical cache memory device 100 having CAM cells, and FIG. 2 is a detailed circuit diagram of a typical CAM cell 200. Referring to FIG. 1, a tag address for a memory cell block 101 is stored in CAMs CAM11 through CAM1n, a tag address for a memory cell block 102 is stored in CAMs CAM21 through CAM2n, and that for a memory cell block 103 is stored in CAMs CAMm1 through CAMmn. Only one of the stored tag addresses will be the same as an address input from a CPU (not shown), so that a xe2x80x98hitxe2x80x99 occurs only once.
A dynamic node CHIT1 is commonly connected to the CAMs CAM11 through CAM1n, and a dynamic node CHIT2 is commonly connected to the CAMs CAM21 through CAM2n. Similarly, a dynamic node CHITm is commonly connected to CAMs CAMm1 through CAMmn.
All of the dynamic nodes CHIT1 through CHITm are initially precharged to a line voltage level. The precharged line voltage level of each dynamic node is maintained if an address input from the CPU is the same as the tag address stored in the related CAMs, i.e., if a xe2x80x98hitxe2x80x99 occurs. If this is not so, i.e., if a xe2x80x98missxe2x80x99 occurs, each dynamic node discharges until reaching a ground voltage level.
For instance, when an n-bit address input from the CPU is the same as a tag address stored in the CAMs CAM11 through CAM1n, the precharged line voltage level of only the dynamic node CHIT1 is maintained and the other dynamic nodes CHIT2 through CHITm discharge until reaching a ground voltage level.
As a result, only a word line driver circuit 104 connected to the dynamic node CHIT1 is enabled, and only a word line WL1 of the memory cell block 101 is activated. Word line driver circuits 105 and 106 connected to the other dynamic nodes CHIT2 and CHITm are disabled, and the word lines WL2 through WLm are inactivated.
A comparison of a tag address with an address input from a CPU using CAMs has a first problem in that it is difficult to know the exact point in time when the comparison has completed according to the structural features of a CAM. This first problem will now be described in detail with reference to the CAM cell 200 shown in FIG. 2. First, an input of a precharge signal PCH having logic xe2x80x980xe2x80x99 causes a precharge PMOS transistor P1 to turn on and a dynamic node CHIT to be precharged to a line voltage level VDD. After a predetermined amount of time, the precharge signal PCH reaches logic xe2x80x981xe2x80x99, which causes the precharge PMOS transistor P1 to turn off and an NMOS transistor N4 to turn on.
If one bit TA of a tag address stored in a CAM cell shown in FIG. 2 is at logic xe2x80x981xe2x80x99 and one bit CA of an address input from a CPU (not shown) is at logic xe2x80x980xe2x80x99, i.e., a complementary bit TAB of the bit TA is at logic xe2x80x980xe2x80x99 and a complementary bit CAB of the bit CA is at logic xe2x80x981xe2x80x99, a transmission gate TM2 is turned on, a transmission gate TM1 is turned off, and a pull-down NMOS transistor N3 is turned on. As a result, the dynamic node CHIT discharges until reaching a ground voltage level VSS.
Meanwhile, if the bit TA of a tag address stored in a CAM cell is at logic xe2x80x981xe2x80x99 and the bit CA of the address input from the CPU is at logic xe2x80x981xe2x80x99, i.e., a complementary bit TAB of the bit TA is at logic xe2x80x980xe2x80x99 and a complementary bit CAB of the bit CA is at logic xe2x80x980xe2x80x99, the transmission gate TM2 is turned on, the transmission gate TM1 is turned off, and a pull-down NMOS transistor N3 is turned off. As a result, the precharged line voltage level of the dynamic node CHIT is maintained.
In other words, in the event that the bit TA of the tag address stored in the CAM cell is not the same as the bit CA of the address input from the CPU, i.e., a xe2x80x98missxe2x80x99 occurs, the dynamic node CHIT discharges until reaching a ground voltage level VSS. However, if the bit TA of the tag address stored in the CAM cell is the same as the bit CA of the address input from the CPU, i.e., a xe2x80x98hitxe2x80x99 occurs, the precharged line voltage level VDD of the dynamic node CHIT is maintained.
In the latter case, i.e., when a xe2x80x98hitxe2x80x99 occurs, a second problem is that it is difficult to know the exact point in time when the comparison of a tag address and an address input from a CPU has completed since the precharged level of the dynamic node CHIT is maintained, i.e., an event due to transition does not occur.
Turning to FIG. 3, a conventional method of solving this second problem is described with respect to a typical cache memory device 300. The device 300 uses a dummy CAM miss path that is made to be always mismatched. Thus, a path having dummy CAM cells 1 through n is commonly connected to a dummy dynamic node Dummy CHIT. The dummy dynamic node Dummy CHIT is commonly connected to word line drivers 304 through 306.
The dummy CAM miss path models the CAM miss path for a worst case scenario so that a xe2x80x98miss hitxe2x80x99 always occurs in the dummy CAM miss path. The CAM miss path for a worst case scenario refers to a CAM miss path having the slowest discharging operation in which only one cell of the CAM cells, which are connected to the dynamic node Dummy CHIT, is discharged.
However, it is difficult to design the dummy CAM miss path completely based on the model of the CAM miss path for the worst case scenario by the conventional method of using the cache memory device of FIG. 3. Even if the dummy miss path completely models the CAM miss path for the worst case during the design of a semiconductor integrated circuit, the timing of the dummy CAM miss path may be not the same as that of the CAM miss path for the worst case scenario, due to a variation in a process of fabricating a semiconductor integrated circuit or variation in temperature. This difference would lower the operational speed of the cache memory device of FIG. 3 using the conventional method.
Also, the conventional method requires the inclusion of a dummy CAM miss path including dummy CAM cells 1 through n into a semiconductor integrated circuit 300 as shown in FIG. 3, thereby increasing the chip area of such a semiconductor integrated circuit.
The present invention provides a cache memory device having a word line driver circuit that is capable of increasing the operational speed of the cache memory device and causing a reduction in the chip area of a semiconductor integrated circuit.
The present invention also provides a method of driving a word line of a cache memory device that increases the operational speed of the cache memory device and causes a reduction in the chip area of a semiconductor integrated circuit.
According to one aspect of the present invention, there is provided a cache memory device including a first memory cell block; a second memory cell block; a plurality of first content addressable memory (xe2x80x9cCAMxe2x80x9d) cells for storing a tag address of the first memory cell block and commonly connected to a first dynamic node; a plurality of second CAM cells for storing a tag address of the second memory cell block and commonly connected to a second dynamic node; and a first word line driver circuit for driving a word line of the first memory cell block in response to signals output from the first and second dynamic nodes.
The cache memory device further includes a second word line driver circuit for driving a word line of the second memory cell block in response to signals output from the first and second dynamic nodes.
The first and second dynamic nodes are initially precharged to a predetermined level. The precharged predetermined level of one of the first and second dynamic nodes is maintained and the other one is discharged, when an address is input from a CPU.
The first word line driver circuit activates the word line of the first memory cell block when the predetermined level of the first dynamic node is maintained and the second dynamic node is discharged. The second word line driver circuit activates the word line of the second memory cell block when the predetermined level of the second dynamic node is maintained and the first dynamic node is discharged.
According to another aspect of the present invention, there is provided a cache memory device including a first memory cell block; a second memory cell block; a third memory cell block; a plurality of first CAM cells for storing a tag address of the first memory cell block and commonly connected to a first dynamic node; a plurality of second CAM cells for storing a tag address of the second memory cell and commonly connected to a second dynamic node; a plurality of third CAM cells for storing a tag address of the third memory cell block and commonly connected to a third dynamic node; a first word line driver circuit for driving a word line of the first memory cell block in response to signals output from the first and second dynamic nodes; and a second word line driver circuit for driving a word line of the second memory cell block in response to signals output from the second and third dynamic nodes.
The cache memory device further includes a plurality of dummy CAM cells connected to a dummy dynamic node; and a third word line driver circuit for driving the third memory cell block in response to signals output from the third dynamic node and the dummy dynamic node.
The first through third dynamic nodes and the dummy dynamic node are initially precharged to a predetermined level. The precharged predetermined level of only one of the first through third dynamic nodes is maintained and the others are discharged when an address is input from a CPU.
The first word line driver circuit activates a word line of the first memory cell block when the predetermined level of the first dynamic node is maintained and the second dynamic node is discharged. The second word line driver circuit activates a word line of the second memory cell block when the predetermined level of the second dynamic node is maintained and the third dynamic node is discharged. The third word line driver circuit activates a word line of the third memory cell block when the predetermined level of the third dynamic node is maintained and the dummy dynamic node is discharged.
According to still another aspect of the present invention, there is provided a method of driving a word line of a cache memory device including a first memory cell block, a second memory cell block, a plurality of first CAM cells for storing a tag address for the first memory cell block and commonly connected to a first dynamic node, and a plurality of second CAM cells for storing a tag address of the second memory cell block and commonly connected to a second dynamic node, the method including initially precharging the first and second dynamic nodes to a predetermined level; maintaining the precharged predetermined level of the first dynamic node when an address input from the CPU is the same as a tag address stored in the plurality of first CAM cells and, in the reverse case, discharging the first dynamic node; maintaining the precharged predetermined level of the second dynamic node when the address input from a CPU is the same as a tag address stored in the plurality of second CAM cells and, in the reverse case, discharging the second dynamic node; and activating a word line of the first memory cell block when the predetermined level of the first dynamic node is maintained and the second dynamic node is discharged. The method further includes activating a word line of the second memory cell block when the predetermined level of the second dynamic node is maintained and the first dynamic node has discharged.
According to still another aspect of the present invention, there is provided a method of driving a word line of a cache memory device including a first memory cell block, a second memory cell block, a third memory cell block, a plurality of first CAM cells for storing a tag address for the first memory cell block and commonly connected to a first dynamic node, a plurality of second CAM cells for storing a tag address of the second memory cell block and commonly connected to a second dynamic node, a plurality of third CAM cells for storing a tag address of the third memory cell block and commonly connected to a third dynamic node, and a plurality of dummy CAM cells commonly connected to a dummy dynamic node, the method including initially precharging the first through third dynamic nodes and the dummy dynamic node to a predetermined level; maintaining the precharged predetermined level of the first dynamic node when an address input from a CPU is the same as a tag address stored in the plurality of first CAM cells and, in the reverse case, discharging the first dynamic node; maintaining the precharged predetermined level of the second dynamic node when the address input from the CPU is the same as a tag address stored in the plurality of second CAM cells and, in the reverse case, discharging the second dynamic node; maintaining the precharged predetermined level of the third dynamic node when the address input from the CPU is the same as a tag address stored in the plurality of third CAM cells and, in the reverse case, discharging the third dynamic node; activating a word line of the first memory cell block when the predetermined level of the first dynamic node is maintained and the second dynamic node is discharged; and activating a word line of the second memory cell block when the predetermined level of the second dynamic node is maintained and the third dynamic node is discharged.
The method further includes maintaining the precharged predetermined level of the dummy dynamic node when the address input from the CPU is the same as a tag address stored in the plurality of dummy CAM cells and, in the reverse case, discharging the dummy dynamic node; and activating a word line of the third memory cell block when the predetermined level of the third dynamic node is maintained and the dummy dynamic node is discharged.